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MXED202
128-Channel OLED Row Driver
Features * CMOS High Voltage Process: 9V-30V Display Panel Supply Compatible * 128 Output Channels, Cascadable; Configurable 120-Output Mode * 150mA Maximum Current Capability per channel (two channels maximum active simultaneously) * 20 Ohm Maximum Row Switch "On" Resistance * Token-Based Control: Bidirectional data transfer; Single and Dual-Token Mode * Current Source Magnitude User Control: 4 A to 1 mA * 6-Bit Monochromatic/Color Gray-Scale User Control * Monochromatic Voltage Precharge Options * 3.3 V to 5 V logic supply * Up to 100kHz clock frequency * Gold-Bumped Die @ ~ 60 micron Output Pitch * TCP packaging * Companion to MXED102 240-Channel OLED Column Driver Description The MXED202 Row Driver supports up to 128-row OLED panel displays. The MXED202 has low "on" switch resistance, and support of voltage precharge options, ensures uniform luminance at rapid row scan rates. This is the first ASSP production row driver for OLED display OEM's, enabling the development and manufacture of this new standard in flat-panel display technology.
For All Passive-Matrix Organic-Light-EmittingDiode Displays * Monochrome and Color * Small-Molecule and Polymer * Common-Cathode Row Switching
Functional Block Diagram
Preliminary
DS-MXED202-R2
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MXED202
PRELIMINARY ELECTRICAL DATA SHEET
Preliminary
The MXED202 is a row-multiplexed display driver, for Passive Matrix Organic Light Emitting Diode (OLED) and Polymer Light Emitting Diode arrays (PLED, PolyLED, LEP, . . .), with anodes connected to current-sourcing column data drivers. The common cathode rows (channels) of the display matrix are activated by sequentially switching them to a low impedance voltage source (ground/0V, typically) in synchronism with the digital data column current drive. The MXED202 supports precharging options to improve luminance control. It is manufactured in a high voltage (30 V) CMOS process and provided in bumped die and TCP (Tape Carrier Package) form.
Overview A row-scan token bit is passed along the length of MXED202 shift register to successively activate the row switches. The OLED cathodes of the active row(s) are switched to RTN, a low impedance return, ground or 0V typically, while the companion column drivers source data-driven currents through each OLED to be illuminated. Inactive rows are connected to a programmable "Off" (or Precharge) voltage to ensure the OLED's are not forward-biased. A programmable precharge interval and programmable precharge voltage are available to set initial conditions for the next active row(s). In normal, or single token mode, the token may be entered at either end of the MXED202 row shift register (SRIN or SLIN), depending on the shift direction selection Shift Right (SHR). The token is shifted one row (one channel) per clock cycle, CLK. One row maximum is active at a time. In dual mode (DUAL), the token is entered at one end and automatically in the center, and again the tokens may be selectively shifted left or right at the CLK rate; two rows maximum are active at a time. The MXED202 has options for 128- and 120-row display panels. When the Select 128 (S128) pin is tied low, the token is also automatically entered at the fifth cell from the entry direction end; only the 120 middle outputs, Rows 4 through 123, should be used. Note that a lesser number of rows may be used by resetting the MXED202 (RSTB) at any time, truncating the shift cycle.
Overview of Operation A row-scan token bit is passed along the length of MXED202 shift register to successively activate the row switches. The OLED cathodes of the active row(s) are switched to RTN, a low impedance return, ground or 0V typically, while the companion column drivers source data-driven currents through each OLED to be illuminated. Three successive row activations, N-1, N, N+1, are depicted in the simplified timing diagram below. Inactive rows are connected to a programmable "Off" (or Precharge) voltage to ensure the OLED's are not forward-biased. A programmable precharge interval and programmable precharge voltage are available to set initial conditions for the next active row(s). Precharge is described on page 9.
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Preliminary
Simplified Timing Diagram
MXED202
Token: The row-scan token(s) activate row switches. Token entry positions, 0 to 127, are defined in the table below:
S128 00 0 1 127,123 127
DUAL * SHR 01 10 0,4 0 127,123,63 127,63
Outputs Used 11 0,4,64 0,64 Rows 4-123 (Rows 0-3, 124-127 N/C) Rows 0-127
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MXED202
PACKAGE AND PINOUT
Preliminary
This drawing illustrates the pin ordering and relative locations of the bond pads, only. Semiconductor Die specification(2) for exact coordinates. Top View:
See the MXED202
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Preliminary
PIN LIST Name RTN GND VCC VMAX I/O/A I I I I Description
MXED202
ReTurN for all display current. (Low impedance ground connection, typically) GrouND, the negative return for all chip current and the digital logic "zero" refer ence level. The logic voltage positive supply. MXED202 logic operates between VCC and VSS. Digital inputs should not exceed VCC, VSS This Voltage MAXimum is the highest positive power supply voltage present on the chip, and supplies the display panel precharge current either directly or at derived voltage VOH. Inputs to the chip should not exceed VMAX to avoid for ward biasing substrate diodes. Row Voltage Output High supply. This pin is normally connected to an external power supply pin VMAX with bypass capacitor, and to pin DRV. Alternatively, an internal amplifier can generate VOH from an input voltage DRV. INVerting input to Voltage Regulator Op Amp, to which an input Resistor RI and feedback Resistor RF may be connected to develop VOH from VDRV; see DRV pin. When not connected to VOH and VMAX, a Drive Reference Voltage >1V can be connected to the DRV pin.Note: If VDRV <0.3V, all row circuitry is powered down. Active high static SHift Right control input: When SHR=1, the token bit travels from R0 to R127, with SRIN being the token input, SLIN the token output. When SHR=0, the token bit travels from R127 to R0, with SLIN being the token input, SRIN the token output. SHR should always be driven to the desired logic level. Shift Right INput. This bi-directional pin is the token input when SHR is high, and the token output (for synchronization or cascading) when SHR is low. When con figured as an input, this pin should always be driven. Normally low, SRIN should be driven high once per frame to enter the token into the shift register. Shift Left INput. This bi-directional pin is the token input when SHR is low, and the token output (for synchron- ization or cascading) when SHR is high. When configured as an input, this pin should always be driven. Normally low, SLIN should be driven high once per frame to enter the token into the shift register. DUAL tokens are seeded into the first and middle shift register cells from SRIN or SLIN when DUAL is static active high. When low, a single token is active. The rising edge of the CLocK input shifts the token along the internal shift regis ter to activate successive rows. The display Row Scan Rate is the CLK frequen cy times the number of tokens. If the PreCharge Bar input is low on the rising edge of CLK, all row outputs will be switched to the same voltage (see MONO) to enable display panel precharg ing until PCB returns high. Holding PCB high disables MXED202 precharge. Enables MXED202 row driver precharge of MONOchromatic displays, if PCB=0. The MONO input has no effect if PCB=1. This input MODifies precharge timing Select 128 row driver output mode when static active high. When low, 120 row driver output mode is selected.
VOH [Page 12] INV [Page 12] DRV [Page 12] SHR
I/O/A
I
I
I
SRIN
I/O
SLIN
I/O
DUAL CLK
I I
PCB [Pages 9-11] MONO [Pages 9-11] MOD [Pages 9-11] S128
I
I I I
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MXED202
Preliminary
Pin List (Continued) ROPT [Pages 10-11] I/O/A Resistor OPTion pin, normally N/C for digitally controlled precharge timing (PCB), or when precharge is disabled. When a resistor R is connected between ROPT and PCB, and a capacitor C is connected between PCB and VSS, the precharge time will be RC/1.65 when measured from the rising edge of CLK to the falling edge of ROPT. The timing components should be selected such that RC/1.65 not exceed 10% of the row active time. ReSeT Bar, static, active low reset input, clears all the shift register cells, elimi nating token content. Row driver outputs. R(0)-R(127) are used in 128 output mode, S128=1. Only R(4)-R(123) should be connected when S128=0. High voltage REFerence is an internally generated PFET switch drive voltage (approximately five-volts less than VOH), which should be bypassed to VOH with a 2200pF external capacitor. Low voltage REFerence is an internally generated NFET switch drive voltage (approximately five-volts above GND), which should be bypassed to GND with a 2200pF external capacitor. Test Pin, N/C Test Pin, N/C
RSTB R(n) HREF
I O O
LREF
O
NRMH NRML
O O
ELECTRICAL SPECIFICATION Note: positive currents flow into the part, negative currents flow out of the part. Absolute Maximum Ratings: Parameter Ambient temp Low voltage supply High voltage supply Operating Conditions: Unless otherwise stated, all parameters are specified for the following operating conditions. Parameter Ambient temp Low voltage supply High voltage supplies Clock Frequency Sym TA VCC VMAX CLK Operating Condition Min 0 3.0 5.0 Typ Max 70 5.5 30 100 Units
o
Operating Condition -
Min -65 -0.3 -0.3
Typ
Max 155 7.0 35.0
Units
o
C
V V
C
V V kHz
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Preliminary
Chip Supply Currents - Exclusive of Load Parameter Logic Supply, Operating Logic Supply, Powerdown High Voltage Supply, Operating High Voltage Supply, Powerdown Sym IVCC IVCC IVMAX IVMAX Operating Condition VDRV>1V, fCLK<100kHz 3V1V, fCLK<100kHz 9VMXED202
Units A A
-
445 -
700 20
A A
Digital Inputs: SHR, SRIN, SLIN, DUAL, CLK, PCB, MONO, S128, RSTB Parameter Input low voltage Input high voltage Input current Clock Rise Time Clock Fall Time Clock Duty Cycle Setup Time Sym VIL VIH II CLKRT CLKFT CLK% TSet Operating Condition Time in advance of 10% rising edge of CLK that inputs SHR, SRIN, SLIN, DUAL, PCB, MONO, S128, CLRB must be at valid input logic levels to take effect on next clock cycle. Time subsequent to 90% rising edge of CLK that inputs SHR, SRIN, SLIN, DUAL, PCB, MONO, S128, CLRB must be valid to take effect on next rising edge of the clock (CLK). 20 50 Min VCC-0.4 -10 Typ Max 0.4 10 5 5 80 Units V V A nS nS % nS
Hold Time
THold
50
-
-
nS
Digital Outputs: SRIN, SLIN, ROPT Parameter Output low voltage Output high voltage Output rise/fall time Precharge Timing Resistor connected to pin ROPT Sym VOL VOH TRF RROPT Operating Condition Iout = 200 A Iout = -200 A 10 to 90 %, Cload = 5 pF Pages 9-11 Min VCC-0.4 50 Typ Max 0.4 5 200 Units V V nS k
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MXED202
Analog Inputs: DRV, INV Parameter DRV Pin Input Resistance DRV Pin Input Capacitance Voltage Range of DRV Input Feedback Resistor from VOH to INV Input Resistor from INV to GND Gain Ratio Sym DRVRin DRVCin VDRV RF RI RF / RI
Preliminary
Operating Condition Min 10 1.0 10 10 0.1 Typ Max 10
VMAX-1.5
Units k pF V k k -
100 100 10
Analog Outputs: VOH, HREF, LREF, R(n) Bypass capacitors to GND: CVOH=10F; CHREF, CLREF =2nF Parameter Precharge Voltage Precharge Ripple Sym VOH VOHac Operating Condition Iout avg= 100 A, CLOAD=1000pF Voltage Regulator Active, Iout avg= 100 A VROW < 5V (to enable OLED turn-on) VROW > (VOH-2V) (to disable OLED turn-on) Per output Min 5 Typ Max 30 100 Units V mV p-p pF
Row 0-127 Output RowON Pulldown Resistance Row 0-127 Output Pullup Resistance Row 0-127 Chip Output Capacitance RowOFF CRow
-
-
20 300 20
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Preliminary
PRECHARGE:
MXED202
(Organic) Light-Emitting Diodes are current controlled devices, their photonic output (luminance) being proportional to the time-average charge passed through them. To pass charge, the forward voltage must first reach the diode "on" threshold. In passive-matrix panel displays, OLED's are connected in n-row x m-column matrix fashion. In the row multiplex scheme, where a single row of OLED's is activated at a time, the parasitic capacitance of the n-1 "off" rows of OLED's appears connected to the columns - this capacitance must be charged to the "on" threshold before current flows through the selected "on" row diodes. If the column drive current alone were to charge this capacitance, much of the allotted row time would be consumed in just reaching the "on" threshold. Therefore, to improve the efficiency of the display, and to make luminance directly proportional to column current-magnitude and currentduty cycle, the MXED102 and MXED202 Display drivers support optional voltage precharge. In all precharge options, a predetermined voltage is impressed upon the diodes. For instance, the user may configure the precharge voltage to be near the OLED "on threshold," to bias the diodes to the onset of conduction. The Timing Diagrams, Pages 10-11, illustrate the Prechage Options: Condition PCB=1 MONO=1 No Precharge A Monochromatic Precharge voltage may be applied via the MXED202 Row Driver, as a function of CLK, PCB, MOD. During the Discharge interval, all Row and Column driver outputs are grounded, discharging all pixels. At the beginning of the Active interval, a selected Precharge Voltage is applied to all but the next active row, and the column drivers source data-driven currents. Color/Monochrome Precharge by the MXED102 Column Driver, as function of CLK, PCB. Precharge
MONO=0
Rev. 2
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MXED202
TIMING DIAGRAMS
Preliminary
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Preliminary
MXED202
Rev. 2
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MXED202
VOH OPTIONS
Preliminary
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Preliminary
SEMICONDUCTOR DIE DATA SHEET
MXED202
The MXED202 is a common cathode (row) driver for Passive Matrix Organic Light Emitting Diode (OLED) and Polymer Light Emitting Diode (PLED, PolyLED, LEP,...etc.) displays, with anodes connected to the columns. This document specificies the physical and mechanical properties of MXED202 semiconductor die, as provided in wafer form. DIMENSIONS Die Size "X Dimensions" Center Scribe to Center Scribe: 8270 m "Y Dimensions" Scribe to Center Scribe: 2300 m Die Thickness Unthinned (Non Back Lapped Wafer) Thickness: 25 mil
Rev. 2
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MXED202
BONDING PADS Locations and Sizes -Driver Outputs
Preliminary
The information contained on this page is preliminary. Although the order of the bond pad will remain the same, the XY dimensions in the final document may vary slightly. Please take this possibility into consideration when doing any chip on board layouts.
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Preliminary
Interface Input/Output
MXED202
Rev. 2
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Clare cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in this Clare product. No circuit patent licenses nor indemnity are expressed or implied. Clare reserves the right to change the specification and circuitry, without notice at any time. The products described in this document are not intended for use in medical implantation or other direct life support applications where malfunction may result in direct physical harm, injury or death to a person.
Specification: DS-MXED202-R2 (c)Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 5/21/01
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